1. Field
The present invention relates to the field of manufacturing of microelectronic devices and microelectromechanical systems (MEMS), and more particularly to the formation of microshells to encapsulate such devices on a substrate.
2. Discussion of Related Art
The term “MEMS” generally refers to an apparatus incorporating some mechanical structure having a dimensional scale that is comparable to microelectronic devices. This mechanical structure is typically capable of some form of mechanical motion and having dimensions below approximately 250 um. Micro-scale fabrication techniques similar to those utilized in the microelectronic industry such as thin film deposition, and thin film patterning by photolithography and reactive ion etching (RIE) form the micromechanical structure in a MEMS.
Many devices, particularly MEMS do not function properly when embedded in a completely solid environment. For example, a MEMS may comprise a resonator or accelerometer fabricated on a substrate, both of which include at least one element that must mechanically move relative to the substrate during operation. Freedom to move during operation would be lost if these elements were simply left embedded in a solid film deposited over the substrate as is commonly done in the microelectronics industry. For this reason, a micromechanical structure must be released from the substrate so that it is not contained within a purely solid environment. A released micromechanical structure is fragile and must be protected with some form of package which isolates a microenvironment surrounding the micromechanical structure from a global environment surrounding the substrate. The package may further be hermetically sealed so that it can remain evacuated or pressurized with a gas or other fluidic media. Similarly, some microelectronic devices (devoid of micromechanical structures) can also benefit from being contained within an isolated micro-environment. For example, a high speed transistor may be suspended in a manner so that it is substantially surrounded by a partial vacuum contained within a chamber so as to reduce parasitic capacitances associated with the relatively high dielectric constant of most solid materials. The type of package employed for such a MEMS or microelectronic device greatly affects their cost and functionality.
One option is encapsulating a device in a conventional “TO can,” well-known in the industry as a standard packaging method for a discrete device. This type of packaging is not wafer-level and is limited to stand-alone (discrete) devices, and therefore is expensive. Another packaging option is the microcap 100 shown in FIG. 1A. Here, first substrate 102 supports device 101. A thick film or second substrate 105 is first aligned and then bonded to first substrate 102 by means of seal ring 110 to form a cap over device 101. Fabrication of microcap packages of the type shown is frequently more expensive than the fabrication of the devices they protect. Fabrication and alignment of second substrate 105 is costly and, as shown, seal ring 110 requires a significant amount of die area, thereby increasing the cost by limiting the minimum dimension of the package. For example, the size of microcap 100, after accommodating packaging alignment and seal ring area, can be nearly twice the area of device 101. Thus, the microcap package limits the scaling of the packaged device, accounts for a large percentage of the packaged device cost and limits wafer-level integration of devices requiring a fluidic environment with those that do not.
Another option is a conventional thin film encapsulated package 150 as shown in FIG. 1B. Here, thin films, such as a low pressure chemical vapor deposition (LPCVD) polycrystalline silicon (polysilicon) or silicon nitride (Si3N4), cover device 101. Unlike the microcap package previously discussed, encapsulation by thin films does not require large seal rings or thick substrate caps and so are commonly referred to as “microshells.” A microshell typically comprises a thin film layer having a perforation and a thin film sealing layer. As shown in FIG. 1B, perforated layer 115 has a perforation 116 from which a sacrificial layer under the perforated layer 115 is removed to expose device 101. Sealing layer 120 then closes perforation 116 to complete the microshell.
Because a thin film is utilized rather than a thick film or substrate, no seal ring is required and misalignment issues are reduced relative to the bonded-cover package. However, one issue with the conventional microshells is that the pressure inside the microshell is not controllable as in the microcap bonding process. Conventional microshells typically rely solely on a sealing layer 120 of silicon dioxide. Sealing the microshell with a silicon dioxide process typically limits the level of vacuum that can be achieved within the microshell and can result in contamination on the encapsulated device. Furthermore, conventional microshells are not as robust as bonded microcap packages and so, as the chamber size is increased, are not readily capable of withstanding the pressure of the final package molding process employed in conventional microelectronics, which is on the order of 1000 pounds per square inch (PSI). Therefore, the cost of the final package encompassing the conventional microshell can remain high. For this reason too, it is not easy to monolithically integrate a conventional microshell with microelectronic devices (eg. CMOS).
Still another limitation of conventional microshells is that non-conventional processes are typically employed which either increase costs or render the package incompatible with microelectronics. For example, accessing the sacrificial layer is typically by way of a high aspect ratio perforation 116 that is first lithographically patterned and then etched through a non-porous pre-sealing layer. This etching of high aspect ratio perforations 116 through a non-porous pre-sealing layer can be very difficult because non-planarity, as shown in FIG. 1B, limits the minimum resolvable aperture diameter for a given exposure wavelength. Moreover, process difficulties associated with etching high aspect ratio apertures (such as etch stop, etc.) increase the cost of forming the high aspect ratio perforation 116 in conventional thin film encapsulated package 150.
Furthermore, many conventional microshells require high temperature processing that is incompatible with microelectronic devices. For example microshells incorporating silicon, such as monocrystalline or polycrystalline silicon, to either form perforated layer 116 or sealing layer 120 require processing temperatures greater than 600° C. Such high temperature processes forecloses the formation of a conventional microshell subsequent to the formation of many microelectronic and/or MEMS. Because modern CMOS transistors typically have a low thermal budget, any processing of a significant duration at much over 650° C. will degrade transistor performance. Thus, integration of a microshell with CMOS can not easily be accomplished. Therefore, high temperature microshell fabrication requires the microshell to be made prior to any transistor fabrication. Thus, monolithically integrating the conventional microshell with microelectronics is again severely limited.